Silicon on insulator device and layout method of the same

ABSTRACT

A silicon on insulator (SOI) semiconductor device includes a wire connected to doped regions formed in an active layer of a SOl substrate. A ratio of the area of the wire to the doped region or a ratio of the area of contact holes formed on the wire to the doped region is limited to a predetermined value. When the ratio exceeds the predetermined value, a dummy doped region is added to prevent the device from being damaged during a plasma process.

INCORPORATION BY REFERENCE

The disclosure of Japanese Patent Application No. 2001-330276 filed onOct. 29, 2001 including the specification, drawings and abstract isincorporated herein by reference in its entirety

BACKGROUND OF THE INVENTION

1. Field of Invention

This invention relates to semiconductor devices fabrication on siliconon insulator (SOI) substrates and to layout methods for suchsemiconductor devices.

2. Description of Related Art

Plasma etching, sputtering, plasma chemical vapor deposition (i.e.,plasma CVD), ion implantation and other plasma processes are widelyemployed in fabrication of semiconductor devices.

During the plasma process, the surface of the semiconductor substrate isirradiated with charged particles (i.e., ions an electrons) in theplasma. When the semiconductor substrate has a metal wire on itssurface, which is not connected to the substrate, electric charges enterand accumulate in the metal wire. In other words, a wire on the surfaceof the substrate acts as an antenna to collect charges from the plasma.

Such accumulated charges induce charging-up and cause damage to thedevices. For example, if a gate electrode of a metal-oxide-semiconductor(MOS) device (MOS transistor) is connected to the metal wire, a gateinsulating film below the gate electrode may be damaged. That is, a highvoltage due to the charging up is applied to the gate insulating filmand thereby degrades the quality of the semiconductor device and,further, causes dielectric breakdown.

Because the amount of accumulated charge increases in proportion to thearea of the wire, the voltage applied to the gate insulating film alsoincreases in proportion to the ratio of the area of the wire to the areaof the gate insulating film. Therefore, when the ratio of the area ofthe wire to the area of the gate insulating film, or an “antenna ratio”,exceeds a certain threshold value, the gate insulating film will bedamaged.

Therefore, in the layout of semiconductor devices including MOStransistors, it is proposed to limit the antenna ratio between the areaof the wire and that of the gate insulating film to be less than apredetermined value so that the gate insulating film is not damagedduring a plasma process. For example, Japanese Unexamined PatentPublications Hei 8-97416 (U.S. Pat. No. 5,744,838), Hei 11-186394, andHei 11-297836 (U.S. Pat. No. 6,421,816) disclose such method.

On the other hand, silicon on insulator (SOI) devices, in which MOStransistors are fabricated in an active layer on an insulatingsubstrate, have been increasingly used in recent years. However,detailed investigation of an influence of the plasma process to the SOIdevice has not been reported.

SUMMARY OF THE INVENTION

Through extensive experimentations, this inventor has discovered that adifferent kind of antenna ratio should be taken into account in thelayout of SOI devices. That is, different from the ratio between an areaof a wire and a area of gate insulating film, which is known todetermine the influence of plasma processes on conventionalsemiconductor devices, this inventor has discovered that a ratio betweenan area of a wire and an area of doped region, such as a source/drainregion of a MOS transistor, mainly determine the influence on SOIdevices.

In various exemplary embodiments according to the invention, asemiconductor device can include a silicon on insulator substrate havingan active layer, at least one doped region formed in the active layerand that constitutes a source/drain region of a MOS transistor and anantenna wire formed in an antenna wiring layer. The antenna wire iselectrically connected to the at least one doped region directly orthrough at least one connecting wire in at least one lower wiring layerbelow the antenna wiring layer. Moreover, a ratio of a total area of theantenna wire to a total area of the at least one doped region is limitedwithin a range so that one of plasma processes to pattern the antennawiring layer and to deposit an interlayer dielectric film covering theantenna wiring layer does not damage the MOS transistor.

The “antenna wiring layer” may be any one of wiring layers in thesemiconductor device that is exposed to plasma during the fabrication ofthe device.

In various exemplary embodiments according to another embodiment of theinvention, a semiconductor device can include a silicon on insulatorsubstrate having an active layer, at least one doped region formed inthe active layer and that constitutes a source/drain region of a MOStransistor, and an antenna wire formed in an antenna wiring layer. Theantenna wire is electrically connected to the at least one doped regiondirectly or through at least one connecting wire in at least one lowerwiring layer below the antenna wiring layer. Moreover, an interlayerdielectric film that covers the antenna wiring layer having at least oneconnection hole for connecting to the antenna wire can be included. Aratio of a total area of the at least one connection hole to a totalarea of the at least one doped region is limited within a range so thata plasma process to form the connecting hole does not damage the MOStransistor.

In various exemplary embodiments according to another embodiment of theinvention, a semiconductor device can include a silicon on insulatorsubstrate having an active layer, at least one doped region formed inthe active layer and an antenna wire formed in an antenna wiring layer.The antenna wire is electrically connected to the at least one dopedregion directly or through at least one first connecting wire in atleast one lower wiring layer below the antenna wiring layer.Furthermore, a dummy doped region can be formed in the active layerelectrically connected to the doped region through at least one secondconnecting wire in the antenna wiring layer and/or in the at least onelower wiring layer.

In various exemplary embodiments according to another embodiment of theinvention, a layout method of a semiconductor device can include thesteps of placing at least one doped region in an active layer of asilicon on insulator substrate, and placing an antenna wire in anantenna wiring layer electrically connected to the at least one dopedregion directly or through at least one first connecting wire in atleast one lower wiring layer below the antenna wiring layer. The layoutmethod can further include, when a ratio of a total area of the antennawire to a total area of the at least one doped region exceeds apredetermined value, performing at least one of: (a) adding a dummydoped region in the active layer electrically connected to the dopedregion through at least one second connecting wire in the antenna wiringlayer and/or in the at least one lower wiring layer; (b) adding ajunction diode electrically connected to the doped region through atleast one second connecting wire in the antenna wiring layer and/or inthe at least one lower wiring layer; (c) dividing the antenna wire intotwo parts and electrically connecting the two parts through a thirdconnecting wire in an upper wiring layer above the antenna wiring layer;and (d) dividing one of the antenna wire and the at least one firstconnecting wire into two parts, and inserting a buffer between the twoparts.

In various exemplary embodiments according to another embodiment of theinvention, a layout method of a semiconductor device can include thesteps of placing at least one doped region in an active layer of asilicon on insulator substrate, placing an antenna wire in an antennawiring layer electrically connected to the at least one doped regiondirectly or through at least one first connecting wire in at least onelower wiring layer below the antenna wiring layer, and placing at leastone connection hole for connecting to the antenna wire. The layoutmethod can further include, when a ratio of a total area of the at leastone connection hole to a total area of the at least one doped regionexceeds a predetermined value, performing at least one of: (a) adding adummy doped region in the active layer electrically connected to thedoped region through at least one second connecting wire in the antennawiring layer and/or in the at least one lower wiring layer; (b) adding ajunction diode electrically connected to the doped region through atleast one second connecting wire in the antenna wiring layer and/or inthe at least one lower wiring layer; (c) dividing the antenna wire intotwo parts and electrically connecting the two parts through a thirdconnecting wire in an upper wiring layer above the antenna wiring layer;and (d) dividing one of the antenna wire and the at least one firstconnecting wire into two parts, and inserting a buffer between the twoparts.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows an exemplary schematic layout of a semiconductor deviceaccording to a layout method of this invention;

FIG. 2 shows another exemplary schematic layout of a semiconductordevice according to the layout method of this invention;

FIG. 3 is an exemplary sectional view of the semiconductor device shownin FIG. 2 as an embodiment of this invention;

FIG. 4 is an exemplary sectional view of a semiconductor device asanother embodiment of this invention;

FIG. 5 shows yet another exemplary schematic layout of a semiconductordevice according to the layout method of this invention;

FIG. 6 shows another exemplary schematic layout of a semiconductordevice according to the layout method of this invention;

FIG. 7 shows another exemplary schematic layout of a semiconductordevice according to the layout method of this invention;

FIGS. 8 to 10 each show a sectional view of a conventional semiconductordevice in which plasma damage occurs on its gate insulating film;

FIG. 11 shows a sectional view of a conventional semiconductor device inwhich plasma damage does not occur on its gate oxide; and

FIG. 12 is a sectional view of a semiconductor device using a SOI waferin which plasma damage occurs on its buried oxide film.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

Before explaining preferred embodiment of this invention, influences ofplasma processes on conventional semiconductor devices, which are formedon a surface of a bulk semiconductor substrate, will be explained.

FIGS. 8 to 10 each show a sectional view illustrating a semiconductordevice including a MOS transistor 69 formed on a surface of a bulksemiconductor substrate 64. In each of the figures, the gate insulatingfilm 76 of a MOS transistor 69 is damaged by plasma. More specifically,FIG. 8 shows a plasma etching process to form a first metal wiringlayer. FIG. 9 shows a plasma etching process to form second levelcontact holes subsequent to the process of FIG. 8. FIG. 10 shows aplasma etching process of a passivation film subsequent to the processof FIG. 9.

With reference to FIG. 8, two MOS transistors 68 and 69 are formed on asurface of a silicon substrate (i.e., a semiconductor substrate) 64 andare separated from each other with a field oxide film 65.

The MOS transistor 68 on the right of the figure includes two dopedregions 72 and 74 on the surface of the silicon substrate 64. Thesedoped regions 72 and 74 serve as a source and a drain of the MOStransistor 68, respectively. The MOS transistor 68 further includes agate electrode 78 over the silicon substrate 64 between the dopedregions 72 and 74. A gate insulating film (i.e., silicon oxide film) 76is formed on the surface of the silicon substrate 64 and the gateelectrode 78 is separated from the substrate 64 by the gate insulatingfilm 76. The gate electrode 78 extends in a direction perpendicular tothe paper plane.

The left MOS transistor 69 has a configuration the same as that of theright MOS transistor 68 except that it is rotated 90° and includes agate electrode 28 extending laterally in the figure.

A first interlayer dielectric film 48 is disposed over the siliconsubstrate 64 having the two MOS transistors 68 and 69 and has a firstlevel contact hole 26. The gate electrode 28 of the left MOS transistor69 is connected via the first level contact hole 26 to a first levelmetal wire 16 disposed on the first interlayer dielectric film 48.

With reference to FIG. 8, a metal film for forming a first metal wiringlayer including the metal wire 16 is deposited, a photoresist pattern 34is formed on the deposited metal film, and plasma etching is performedusing the photoresist pattern 34 as a mask.

In the plasma etching process, charged particles in the plasma enterinto the metal film. Specifically, during an over etching after the wire16 is separated from other portions of the metal film, charged particlesenter into the metal wire 16 from the side surfaces of the metal wire 16formed by the etching. The charges accumulate in the metal wire 16, thefirst contact hole 26, and the gate electrode 28 of the MOS transistor69.

That is, the metal wire 16 acts as an antenna to collect charges duringthe etching or patterning of the first metal wiring layer. In otherwords, the first wiring layer is the antenna wiring layer, and the metalwire 16 is the antenna wire during the plasma etching of the firstwiring layer. The amount of accumulated charges increases in accordancewith the increase of the area of the side surfaces of the metal wire 16.If the amount of the accumulated charges exceeds a critical value, thegate insulating film 76 under the gate electrode 28 is damaged ordestroyed.

With reference to FIG. 9, a second interlayer dielectric film 80 isformed over the surface of the semiconductor device carrying the metalwire 16 formed in the process step of FIG. 8. A photoresist pattern 82is formed on the second interlayer dielectric film 80, and the secondinterlayer dielectric film 80 is subjected to a plasma etching using thephotoresist pattern 82 as a mask. Thereby, a plurality of second levelcontact holes 54 is opened.

During an over etching of the plasma etching to open the second levelcontact holes 54, i.e., after a surface of the first level metal wire 16is exposed at the bottoms of the second level contact holes 54, thecharged particles enter the exposed surface of the first level metalwire 16. Charges accumulate in the first level metal wiring 16, thefirst level contact hole 26, and the gate electrode 28 of the left MOStransistor 69.

That is, the exposed portions of the first level metal wire 16 acts asan antenna during the plasma etching to open the contact holes 54. Inother words, the first wiring layer is the antenna, wiring layer, andthe first level metal wire 16 is the antenna wire during the plasmaetching to open the second level contact holes 54. The amount ofaccumulated charges increases in accordance with the area of the secondlevel contact holes 54. If the amount of the accumulated charges exceedsa critical value, the gate insulating film 76 below the gate electrode28 is damaged or destroyed.

Next, with reference to FIG. 10, a metal wire 86 in the second metalwiring layer serving as a pad is formed over the second interlayerdielectric film 80 including the second level contact hole 54 formed inthe process of FIG. 9. A passivation film 88 is then formed over thesurface of the semiconductor device carrying the second level metal wire86. A photoresist pattern 90 is formed on the passivation film 88, andthe passivation film 88 is subjected to plasma etching using thephotoresist pattern 90 as a mask to open a pad opening 58.

In this plasma etching process, charged particles enter a surface of themetal wire 86 exposed at the bottom of the pad opening 58, and chargesaccumulate in the second level metal wire 86, the second level contactholes 54, the first level metal wire 16, the first level contact hole26, and the gate electrode 28 of the left MOS transistor 69.

That is, the exposed portions of the metal wire 86 acts as an antennaduring the plasma etching to open the pad opening 58. In other words,the second wiring layer is the antenna wiring layer, and the secondlevel wire 86 is the antenna wire during the plasma etching to open thepad opening 58. The amount of accumulated charge increases in accordancewith the area of the pad opening 58. If the amount of accumulatedcharges exceeds a critical value, the gate insulating film 76 under thegate electrode 28 is damaged or destroyed.

In this manner, a metal wire exposed to plasma serves as an antenna tocollect charges from the plasma. Accordingly, a gate insulating film 76is markedly damaged or destroyed when an area of a metal wire, which isconnected to the gate electrode directly (i.e., only through a contacthole) or through another wire in one or more lower wiring layers, isincreased. This phenomenon is generally called “an antenna effect”. Thearea of the metal wire may be an area of an upper surface, sidesurfaces, or the both, of the wire, or an area of connection holes forconnecting to the metal wire such as contact holes and pad openingsformed on the metal wire, depending on the process sequence.

To prevent or minimize the damage induced by the antenna effect, a socalled antenna rule is proposed. That is, a ratio (i.e., antenna ratio)between an area of a metal wire, which is connected to a gate electrodeand acts as an antenna during a plasma process, and an area of the gateelectrode is limited to equal to or lower than a predetermined value. Ifthe ratio exceeds the predetermined value, a protective device such as aresistor or a diode is attached to the gate electrode.

This conventional antenna rule only applies to the case where the metalwire is not connected to the semiconductor substrate.

With reference to FIG. 11, the metal wire 16 of the first metal wiringlayer is connected to a doped region 74 on the surface of thesemiconductor substrate 64. Then, charges entered from the plasma flowthrough the doped region 74 into the silicon substrate 64. Thus, a highvoltage is not applied to the gate electrode 28, and thereby the gateinsulating film 76 is not damaged.

It was discovered that, however, the situation is completely differentin a SOI device.

Next, the influence of a plasma process on a SOI device will beexplained.

FIG. 12 shows an example of SOI semiconductor device, in which two MOStransistors 68 and 69 are formed on an active layer 35 of an SOIsubstrate 37. The SOI substrate 37 has the active layer 35, a siliconsubstrate 38, and a buried oxide film 36 between the active layer 35 andthe silicon substrate 38. A MOS transistor 68 is formed of a gateelectrode 28, a gate insulating film 76, and doped regions 25 and 27formed in the active layer 35.

As can be seen from FIG. 12, the doped region 74 is isolated from thesilicon substrate 38 by the buried oxide film 36. Therefore, even thoughthe metal wire 16 is connected to the doped-region 25, the chargesentered from the plasma do not flow into the substrate 38.

Moreover, it was discovered that the buried oxide film 36 is far moresusceptible to the plasma damage than the gate insulating film 76. Thatis, the buried oxide film 36 may be seriously damaged even in cases thatthe gate insulating film 76 connected to the metal wire 16 is notsignificantly damaged.

This discovery is truly unexpected because the buried oxide film is farthicker than the gate insulating film. For a 0.2 μm design rule device,for example, the thickness of the buried oxide is about 100 nm or more,while the thickness of the gate insulating film is about 5 nm. That is,the buried oxide film is far more susceptible to the damage comparedwith the gate insulating film, even though the buried oxide film is morethan 20 times thicker than the gate insulating film.

When the doped region constitutes a source/drain region of a MOStransistor as shown in FIG. 12, even a relatively small charging up thatdoes not seriously damage the buried oxide film may damage the MOStransistor. That is, degradations of properties of the MOS transistorsuch as an increase of a leakage current between the source and drainregions, a change of the threshold voltage, and other problems mayoccur.

Thus, it has become evident that improved SOI devices that are preventedfrom being damaged by a plasma process are highly desired. Layoutmethods for providing such improved SOI devices are also highly desired.

Now, preferred embodiments of the semiconductor devices and layoutmethods for such semiconductor devices of this invention will beexplained with reference to the attached drawings.

FIG. 1 is an exemplary schematic layout of semiconductor device designedby the layout method of this invention.

With reference to FIG. 1, a semiconductor device 10 is a SOI deviceincluding MOS transistors formed on a surface of a SOI substrate.Specifically, two complementary MOS (CMOS) inverters 12 and 14 arearranged at a predetermined spacing and are connected with each other inseries through a wire 16 in the antenna wiring layer. Each of theinverters 12 and 14 has P-type and N-type MOS transistors (MOSFETs) 18and 20.

The SOI substrate has an active layer (i.e., semiconductor layer)insulated from a semiconductor substrate by a buried oxide film. Each ofthe MOS transistors has two doped regions constituting source/drainregions formed in the active layer of the SOI substrate. The SOIsubstrate may be formed by various methods such as Separation byImplanted Oxygen (SIMOX).

In each of the inverters 12 and 14, a gate electrode 28 is arranged topass over a P-type and a N-type active region 21 and 23, which areregions of the active layer separated by the field isolation film.P-type and N-type doped regions 22 and 24 are formed on both sides ofthe gate electrode 28. The doped regions 22 and 24 on the left of thegate electrode 28 form source regions of the MOS transistors. The dopedregions 22 and 24 on the right of the gate electrode 28 form drainregions of the MOS transistors. The source regions of the P-type andN-type MOS transistors are connected to a power-supply wiring and aground wiring, respectively, via respective connection holes (firstlevel contact holes) 26. Drain regions of the P-type and N-type MOStransistors are both connected to the first level metal wire 16 viarespective first level contact holes 26.

In the semiconductor device 10 shown in FIG. 1, the ratio of the totalarea of the first level metal wire 16 to the total area of the P-typeand N-type doped regions 22 and 24 connected to the first level metalwire 16, or the drain regions, is limited equal to or less than apredetermined value. As a result, damage, or a degradation ofproperties, of the P-type and N-type MOSFETs 18 and 20 during theprocessing (patterning) of the first level metal wire 16 is prevented.Damage during the plasma process for depositing the first interlayerdielectric film 48 (see FIG. 3) to cover the first level metal wire 16is also prevented.

The term “total area of the first level metal wire 16” herein means atotal area of the first level metal wire 16 exposed to plasma during aspecific plasma process. That is, it means a total area of side surfacesin the process of patterning the first level metal wire 16, and a totalof the top surface and side surfaces of the first level metal wire 16 inthe process of depositing the second interlayer dielectric film coveringthe first level metal wire.

When a plurality of first level metal wires is connected in common to adoped region or doped regions, the total area of the metal wire is a sumof the areas for the plurality of metal wires. The term “area of theP-type and N-type doped regions 22 and 24” means a total top surfacearea of the doped regions 22 and 24 arranged in the active layer of theSOI wafer and connected to the first level metal wire 16 via the firstlevel contact holes 26.

According to this embodiment, the ratio (i.e., antenna ratio) of thetotal area of the side surfaces of the first level metal wire 16 to thetotal area of the P-type and N-type doped regions 22 and 24 of theinverters 12 and 14 is set to be 100:1 or below. Accordingly, when thetotal area of the drain regions 22 and 24 of the inverters 12 and 14 is4 μm², the upper limit of the total area of the first level metal wire16 is 400 μm². If the first level metal wire 16 has a thickness of 0.4μm, the length of the wire is limited equal to or less than 500 μm,i.e., 400/(0.4×2) μm.

By limiting the ratio of the total area of the first level metal wire 16to the total area of the doped regions connected to the first levelmetal wire 16 equal to or less than a predetermined value, chargesaccumulated in the first level metal wire 16 and the doped regions 22and 24 can be suppressed to or less than a certain value. Thus, theinvention can prevent degradation of the properties of the P-type andN-type MOSFETs 18 and 20 during plasma processes such as the patterningstep of the first wiring layer and the deposition step of the secondinterlayer dielectric film 80 (see FIG. 9).

FIG. 2 shows an exemplary schematic layout of another semiconductordevice designed by the layout method of this invention.

With reference to FIG. 2, a semiconductor device 30 further includes adummy doped region 32 in addition to the configuration of thesemiconductor device 10 shown in FIG. 1.

The dummy doped region 32 is connected via a first level contact hole 26to the first level metal wire 16, which connects between the twoinverters 12 and 14. That is, the dummy doped region 32 is electricallyconnected in parallel with the doped regions 22 and 24 of the firstinverter 12. The dummy doped region 32 is used as a capacitor elementhaving a capacitance between the dummy doped region 32 and thesemiconductor substrate 38.

U.S. Pat. No. 5,744,838 proposes to interpose a doped region, whichfunctions as a diode and a resistor, between a gate electrode of atransistor and a wire for transmitting a signal from a preceding stageto prevent plasma damage in a conventional semiconductor device. In thiscase, the wire is divided into two parts and the doped region isconnected in series with the two divided parts. That is, the dopedregion is connected to both of the divide parts of the wire, and isconnected to both of the preceding stage and the gate electrode throughrespective parts of the divided wire.

In contrast, the dummy doped region 32 in the exemplary semiconductordevice shown in FIG. 2 is connected in parallel with the doped regions22 and 24 without cutting the wire 16. Therefore, the dummy doped region32 does not function as a resistor. Further, the dummy doped region 32is isolated from the silicon substrate 38 by the buried oxide film anddoes not function as a diode. That is, the dummy doped region 32 is usedonly as a capacitor element.

The dummy doped region 32 is connected to satisfy the limitation of theantenna ratio when it is determined that following first and/or secondratios exceed predetermined values respectively determined. The firstratio is a ratio of the total area of the first level metal wire 16 tothe total area of the doped regions 22 and 24. The second ratio is aratio of the total area of contact holes 54 arranged on the first levelmetal wire 16 to the total area of the doped regions 22 and 24.

By adding the dummy doped region 32, the total area of the dopedregions, which is the sum of the areas of the doped region 22 and 24 andthe area of the dummy doped region 32, is increased. And the antennaratio is reduced to or less than the predetermined value.

In portions of the semiconductor device where the ratios highly possiblyexceed the predetermined value, it is acceptable to connect the dummydoped regions 32 or other measures to reduce the antenna ratios withoutdetermination whether or not the ratios actually exceed thepredetermined value. By this procedure, the degradation due to theplasma damage does not occur even when the ratios without the dummydoped regions actually exceed the predetermined value.

For example, a wire connecting between an output terminal of a circuitblock in a semiconductor device and an input terminal of another circuitblock of the same semiconductor device has a length of equal to or morethan several millimeters in many cases. Accordingly, the ratio of thearea of a wire connected to an output terminal to the area of dopedregions of MOS transistors constituting the output terminal highlypossibly exceeds the predetermined value.

FIG. 3 is an exemplary sectional view corresponding to the layout shownin FIG. 2. During the patterning step of the first metal wiring layerusing a photoresist pattern 34 as a mask, charged particles enter theside faces of the patterned metal wire 16. The incident chargesaccumulate in the capacitor formed between the doped regions 25 (22 and24) and the silicon substrate 38 to thereby apply a voltage across theburied oxide film 36. In this example, the bottom of the doped region 25reaches the upper surface of the buried oxide film 36. Therefore, thevoltage developed by the charge accumulation directly applies across theburied oxide film 36.

By adding the dummy doped region 32 in parallel with the doped regions25 (i.e., the P-type and N-type drain doped regions 22 and 24 of theMOSFETs in the CMOS inverter 12), the total area of the doped regionscan be increased. In other words, the antenna ratio determined by thearea of the wire 16 and the total area of doped regions, which is a sumof the areas of the doped regions 25 and that of the dummy doped region32, can thereby be reduced.

By increasing the total area of the doped regions, the total capacitancebetween the doped regions and the silicon substrate 38 can be increased.If an amount of electric charges entered during the plasma process isconstant, the voltage applied to the buried oxide film 36 decreases byincreasing the capacitor. Therefore, adding the dummy doped region 32can prevent the degradation of the MOS transistor by decreasing thevoltage applied to the buried oxide film 36.

The number of the dummy doped region 32 is not limited to one, and aplurality of dummy doped regions 32 can be connected in parallel to asingle first level metal wire 16. When the area of the doped regions 22and 24 is large enough, it is also possible to connect the dummy dopedregion 32 through another first level metal wire 16 via another firstlevel contact hole 26.

Alternatively, a diode may be connected to the doped regions 22 and 24instead of the dummy doped region 32.

Referring to FIG. 4, a semiconductor device 40 includes a diode (PNjunction) formed between a doped region 39 and the substrate 38. In FIG.4, an N-type doped region 39 is formed in the surface of a P-typesubstrate, as an example. The diode is electrically connected to thedoped regions 22 and 24 through the first level metal wire 16.

The semiconductor device 40 having N-type doped region 39 can be formed,for example, by following process steps.

First, a field isolation film 66 is formed in the active layer 35 toseparate the active layer 35 into a plurality of active regions forforming respective MOS transistors. The field isolation film 66 may beformed by selectively oxidizing portions of the active layer 35.Alternatively, portions of the active layer may be removed and theremoved portions are filled with, for example, a silicon oxide filmdeposited by chemical vapor deposition. Usually, the field isolationfilm 66 has a thickness such that the bottom of the field isolation filmreaches the upper surface of the buried oxide film 36. In other words,the active layer 35 is completely oxidized or removed in the portionwhere the field isolation film 66 is formed.

Then, a gate insulating film 76 is formed on the surfaces of the activeregions, and gate electrodes 28 and their sidewalls 29 of MOStransistors 68 and 69 are formed.

Next, a field isolation film 66 and a buried oxide film 36 in a portionwhere the N-type doped region 39 is to be formed are etched to form anopening. The field isolation film 66 and the buried oxide film 36 may beeasily removed by a conventional oxide etching process, if the activelayer is completely oxidized or removed during the field oxide formationstep.

The N-type doped region 39 is then formed on the surface of thesubstrate 38 at the bottom of the opening simultaneously with N-typedoped regions 24 constituting source/drain regions of the N-channel MOStransistors 68 and 69. Subsequently, an interlayer dielectric film 48 isdeposited to cover the MOS transistors 68 and 69 and to fill the openingformed in the buried oxide film 36 and in the active layer 35. Firstlevel contact holes 26 for connecting to the source/drain regions orgate electrodes of the MOS transistors 68 and 69, and to the dopedregion 39 are simultaneously formed in the interlayer dielectric film48.

The PN junction diode formed between the silicon substrate 38 and theN-type doped region 39 is connected in parallel to the capacitor formedbetween the doped regions 22 and 24 and the silicon substrate 38. When avoltage applied to the capacitor formed between the doped regions 22 and24 and the silicon substrate 38 increases with increasing amount ofelectric charges entered and accumulated during the plasma process,electric current passes through the PN junction to thereby discharge theaccumulated electric charges. Consequently, the voltage applied to theburied oxide 36 decreases to thereby prevent its dielectric breakdown.

Instead of adding the dummy doped region 32 or the junction diode, it isalso acceptable to divide the first level metal wire 16 in two parts andto insert a buffer 42 between the divided parts.

Referring to FIG. 5, a semiconductor device 50 includes a buffer 42. Thebuffer 42 includes two MOS inverters 44 and 46 connected in series, anddoes not alter the logic. Dividing the first level metal wire 16 in twoparts decreases the antenna ratio.

The number of the buffer 42 is not limited to one, and a plurality ofbuffers 42 may be connected in series between the inverters 12 and 14.If it is necessary to decrease the antenna ratio to or less than thepredetermined value, the first level metal wire 16 may be divided inthree or more parts and a plurality of buffers 42 may be insertedbetween the divided parts.

When the dummy doped region 32 is connected to the first level metalwire 16, an additional capacitance is added to the signal pass betweenthe inverters 12 and 14. Therefore, a signal propagation delayincreases. In contrast, the addition of the buffer 42 does not causesuch increase of the signal propagation delay. However, the addition ofthe buffer 42 requires a larger area than that in the case of adding thedummy doped region 32.

Instead of adding the buffer 42 to the metal wire 16, it is alsoacceptable to divide the metal wire 16 into two parts and to connect thedivided parts through a wire in an upper wiring layer above the firstmetal wiring layer. In this case, the wire of the upper wiring layerdoes not exist and the first level metal wire 16 is electrically dividedwhen the first metal wiring layer is processed. Therefore, the antennaratio is decreased and the amount of charges accumulated during theprocess is decreased.

FIG. 6 shows another schematic layout of a semiconductor device formedon a SOI substrate. The semiconductor device 60 has doped regions formedin the active layer 35 isolated from the silicon substrate 38 by aburied oxide film 36 (See FIG. 3).

The semiconductor device 60 includes a CMOS inverter 52 connected to apad 56 through a first level metal wire 16. The inverter 52 has the sameconfiguration as the inverters 12 and 14 shown in FIG. 1.

The pad 56 serves as an electrode to input and/or output signals to orfrom the semiconductor device 60. Square-shaped portions of the firstlevel metal wire and a second level metal wire, which is stacked overthe first level metal wire, form the pad 56. The second level contactholes 54 for connecting the first level metal wire to the second levelmetal wire are arranged along the periphery of the pad 56. A passivationfilm 88 (see FIG. 10) covers all over the upper surface of thesemiconductor device 60 and is etched in a portion above the pad 56 toform a connection hole (i.e., pad opening) 58.

In the semiconductor device 60, the ratio (i.e., antenna ratio) of thetotal area of the second level contact holes 54 disposed over the firstlevel metal wire 16 to the total area of the doped regions (P-type andN-type drain doped region 22 and 24) of the inverter 52 is limited equalto or less than a predetermined value. Thereby, the damage to theMOSFETs 18 and 20 during the process for forming the second levelcontact holes 54 is prevented.

When the second level contact holes have a fixed size, the upper limitof the antenna ratio may be set by the ratio between the number of thesecond level contact holes and the total area of the doped regions.

The plasma process that is used to-form the contact hole includes aplasma etching of the second interlayer dielectric film 80 to formopenings, a sputter etching to clean the surface of the first levelmetal wire exposed at the bottoms of the openings, and a sputtering todeposit a metal film in the openings. In any process, the total area ofthe second level contact holes 54 to be limited by the antenna rule isthe total area of bottoms of the second level contact holes 54 on thefirst level metal wire 16.

The ratio of the area of the pad opening 58 to the P-type and N-typedrain doped regions 22 and 24 is also limited equal to or less than apredetermined value. Thereby, damage to the P-type and N-type MOSFETs 18and 20 during plasma processes for forming the pad opening 58 isprevented.

In this embodiment, the ratio of the number of the second level contactholes 54 to the total area of the P-type and N-type drain doped regions22 and 24 is limited to five per 1 μm² or less. The ratio of the area ofthe pad opening 58 to the total area of the P-type and N-type draindoped regions 22 and 24 is limited to 100:1 or less. Accordingly, whenthe total area of the P-type and N-type drain doped regions 22 and 24 is20 μm², the upper limits of the number of the second level contact holes54 and the area of the pad opening 58 are 100 and 2000 μm²,respectively.

By limiting the ratio of the total area of the second level contactholes 54 or the total area of the pad opening 58 to the total area ofthe P-type and N-type drain doped regions 22 and 24, the properties ofthe P-type and N-type MOSFETs 18 and 20 can be prevented from beingdegraded during plasma processes.

FIG. 7 shows an exemplary schematic layout of another semiconductordevice designed by the layout method of this invention. Thesemiconductor device 70 of FIG. 7 further includes a dummy doped region62 in addition to the configuration of the semiconductor device 60 ofFIG. 6.

In order the save the surface area of the SOI substrate, the dummy dopedregion 62 is placed below the pad 56. First level contact holes 26 arearranged over the dummy doped region 62 to connect the dummy dopedregion to the first level metal wire 16.

The dummy doped region 62 is thereby connected in parallel with thedoped regions 22 and 24 through the first level metal wire 16, andserves as a capacitor element.

The dummy doped region 62 is added when one of following four ratiosexceed predetermined values respectively determined. The first ratio isthe ratio of the total area of the first level metal wire 16 to thetotal area of the doped regions 22 and 24. The second ratio is the ratioof the total area of the second level contact holes 54 on the firstlevel metal wire 16 to the total area of the doped regions 22 and 24.The third ratio is the ration of the total area of the second levelmetal wire for forming the pad 56, which is connected to the dopedregions 22 and 24 through the first level wire 16, to the total area ofthe doped regions 22 and 24. And the fourth ratio is the ratio of thetotal area of the pad opening 58 to the total area of the doped regions22 and 24.

By connecting the dummy doped region 62 to the first metal wiring 16 inparallel with the P-type and N-type doped regions 22 and 24, the totalcapacitance increases to thereby reduce the antenna ratio.

Alternatively, a diode (PN junction) such as shown in FIG. 4 can beadded instead of the dummy doped region 62.

The above embodiments have been illustrated by mainly taking the firstlevel metal wire 16 as an example of an antenna to collect electriccharges from plasma. In this case, the metal wire 16 is directly (i.e.,only through a first level contact hole 26) connected to one or moredoped regions 25. However, this invention can also be applied to thecases in which metal or other conductive wires in different wiringlayers act as antennas.

When a semiconductor device has two or more metal wiring layers, a wirethat acts as an antenna (an antenna wire) in an upper wiring layer(antenna wiring layer) exposed to plasma may be electrically connectedto a doped region of a MOS transistor through one or more wires (firstconnecting wires) in one or more lower wiring layers. In some cases, aplurality of antenna wires in a same wiring layer is connected thoughone or more lower level metal wires to the same doped region or regions.In this case, the antenna ratio is determined based on the total area ofthe plurality of antenna wires in the same wiring layer.

When a dummy doped region or a junction diode is employed to reduce theantenna ratio, the dummy doped region or a junction diode is connectedto the doped region through one or more wires (second connecting wires)in the one or more lower wiring layers. A wire in the antenna wiringlayer, including the antenna wire itself, may also be used as a secondconnecting wire. Some or all of the first connecting wires may also beused as the second connecting wires.

When a buffer is employed to reduce the antenna ratio, any one of theantenna wire and the first connecting wires may be divided to insert thebuffer.

Materials for wires of this invention are not specifically limited andinclude aluminum, tungsten, and other metals, as well as silicide,polycide, and other conductive materials.

The predetermined values of the antenna ratios highly depend on thespecifications of the SOI wafer such as thickness of the buried oxidefilm, the type of a manufacturing apparatus used in plasma processes andmanufacturing conditions. The values are not limited to the specificvalues described as examples in the embodiments. They can be determinedappropriately to prevent the damage of the buried oxide film andMOSFETs.

To design a layout of an actual semiconductor device, the antenna ratiois automatically calculated. Portions of the layout where the determinedratios exceed the predetermined value are automatically extracted usingan automatic placing and routing system as shown in U.S. Pat. No.6,421,816, which is incorporated by reference in its entirety. Theseprocedures are performed after placing circuit blocks (cells) andarranging routings between the circuit blocks. Thereafter, the automaticplacing and routing system automatically select appropriate measures tosatisfy the antenna rule in the extracted portions. It is also possiblethat an operator selects the appropriate measures.

The “total area” used in the determination of the antenna ratio may bedifferent in different plasma processes. It is the total area of theside surfaces of the first level metal wire 16 in the patterning of thefirst level metal wire, while it is the total area of the upper and sidesurfaces of the first level metal wire 16 in the deposition of thesecond interlayer dielectric film over the first level metal wire 16.

The antenna ratios are preferably calculated for both of the total areasand are compared with respectively determined predetermined values. Whenplasma damage in one of the patterning and the deposition steps is farlarger than that in the other, the total area corresponding to theprocess causing larger plasma damage alone can be calculated andcompared with the predetermined value.

Alternatively, two antenna ratios can be separately calculated for thetotal areas of the upper surface and the side surfaces of the wire. Andthe calculated ratios can be compared with the predetermined values setin view of the damage due to both of the patterning and depositionsteps.

Usually, the thickness of each wiring layer is fixed depending on afabrication process used. Therefore, the area of the side surfaces canbe calculated by the fixed thickness and the perimeter of the wire. Inaddition, the length of the wire can approximately determine the area ofthe side surfaces. Likewise, the length of wire can approximatelydetermine the area of the upper surface when the width of the wire issubstantially constant.

Accordingly, the calculation of the ratio of the total area of the wireto the area of the doped regions and its comparison with thepredetermined value can be approximately substituted with thecalculation of the ratio of the length of wire to the area of the dopedregions and its comparison with a predetermined value set for thatratio.

The antenna ratio can be calculated for the overall semiconductor deviceor for portions where the antenna ratio may highly possibly exceed thepredetermined value. For example, as explained previously, wiresconnecting between output terminals of circuit blocks and inputterminals of different circuit blocks are likely to be very long, andare highly likely to have high antenna ratios. In this case, the antennaratios can be approximately calculated by using the lengths of the wiresof each wiring layer connected to the output terminals, because most ofthe MOS transistors constituting output terminals of the circuit blockshave almost the same size and therefore include doped regions havingnearly the same area.

As explained previously, any one of the wiring layers that is exposed toplasma during the fabrication may become an antenna wiring layer.Therefore, antenna ratios can be calculated for wires in each wiringlayer. Alternatively, antenna ratios can be calculated only for wires inselected layers where the antenna ratio may highly possibly exceed thepredetermined value. For example, the long wires between circuit blocks,which are likely to have high antenna ratios, are usually formed in oneor a few upper most wiring layers.

In short, it is not always necessary to calculate the exact value of theantenna ratio. The antenna ratio can be efficiently calculated by usingvarious practical approximation procedures and can be compared withpredetermined value set with margins according to the approximationprocedure employed, as long as the damage due to plasma processes can beprevented.

The semiconductor devices according to the present invention can beprevented from damaging due to charging up during plasma processes andyield high reliability and improved production yields.

According to the layout method of this invention, the antenna ratio canbe reduced and thereby the limitations on circuit design can besignificantly decreased.

FIG. 4 illustrates, as an example, a semiconductor device in which adoped region 39 having a conductivity type opposite to that of thesemiconductor substrate 38 is formed on the surface of the substrate 38.The doped region 39 is used to forms a diode for preventing thesemiconductor device from being damaged during a plasma process.

Alternatively, doped region having the same conductivity type as that ofthe substrate can be formed on the surface of the substrate in a similarmanner. The doped region of the same conductivity type can be connectedthrough the first contact hole 26, the first level metal wire 16 and ametal wire in an upper wiring layer to a pad. The doped region canfurther be connected via a pad to a terminal of a package housing thesemiconductor device. By using the terminal connected to the dopedregion as grounding terminal or a terminal for applying a specificvoltage, the potential of the substrate can be fixed.

When a conventional semiconductor device using a SOI wafer is housed ina package in which the backside of the substrate is not connected to apackage terminal, such as a flip chip ball grid array (BGA) package, thepotential of the substrate cannot be fixed. Thus causing unstableoperation of the semiconductor device due to a varying potential of thesubstrate.

Forming a doped region having the same conductivity type on the surfaceof the semiconductor substrate and connecting the doped region to aterminal of the package solve this problem while utilizing theconventional packaging technology.

The semiconductor devices and layout methods of semiconductor devices ofthis invention have basic configurations as above. While the inventionhas been described with reference to preferred embodiments thereof, itis to be understood that the invention is not limited to the preferredembodiments or constructions. To the contrary, the invention is intendedto cover various modifications and equipment arrangements. In addition,while the various elements of the preferred embodiments are shown invarious combinations and configurations, which are exemplary, othercombinations and configurations, including more, less or only a singleelement, are also within the spirit and scope of the invention.

1. A method of forming a silicon on insulator device that includes a MOStransistor, the method comprising: providing a silicon on insulatorsubstrate having a semiconductor substrate and an active layer isolatedfrom the semiconductor substrate by a buried oxide film; forming a fieldoxide film in the active layer; removing a portion of the field oxidefilm and a corresponding portion of the buried oxide film to form anopening to expose a portion of a surface of the semiconductor substrate;and simultaneously forming a doped region in the exposed portion of thesurface of the semiconductor substrate and a source and a drain regionof the MOS transistor in the active layer.
 2. The method according toclaim 1, wherein the field oxide film is formed such that a bottom ofthe field oxide film reaches the buried oxide film.